This application claims the priority of Korean Patent Application No. 10-2003-0086288 filed on Dec. 1, 2003 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device, write control circuit and a write control method for the same. More particularly, exemplary embodiments of the present invention relate to a semiconductor memory device which may detect write failures and a write control method for the same.
2. Description of the Related Art
A synchronous semiconductor memory device, for example, a single data rate synchronous dynamic random access memory and/or a double data rate dynamic random access memory, may be synchronized with an external system clock which may improve the access time of semiconductor devices.
Data writing and/or reading may be controlled by a system clock signal which may be input from an external system. As the frequency of external system clocks may increase, the operating speed of a synchronous semiconductor memory device may also increase. A semiconductor testing apparatus for testing such high-speed devices may control the operation times.
After completing the fabrication processes of semiconductor memory devices, a semiconductor memory device test, in which various characteristics of each semiconductor memory device may be evaluated, may be performed before packaging, for example, performing a sawing process.
The semiconductor memory device test may be performed to detect defects which may occur in a fabrication process, for example, in a wafer level or a package level, such that defective products may be screened out.
When a fabrication defect may be detected and/or when the functions of the semiconductor memory device may not satisfy desired specifications, failure analysis may be executed to examine causes of failure, which may enhance the throughput of semiconductor memory devices.
The semiconductor memory device test may be performed in a plurality of ways. For example, direct current (DC) characteristics and/or alternating current (AC) characteristics of semiconductor memory devices may be measured using testing equipment. A voltage may be applied to each electrode of the semiconductor memory device to measure a current, and/or a current may be applied to measure a voltage, which may enable the evaluation of the stability of the power wiring, current consumption, leakage current, etc. in the semiconductor memory device.
In the semiconductor memory device test, a function test may be performed, which may test operations of writing data to and/or reading data from a memory cell.
To test a write operation of a semiconductor memory device, a write recovery time (referred to as tWR) may be defined, and various write failures (for example, a contact resistance failure of a column line select signal) may be detected during the tWR.
The tWR may be defined as a period of time from the beginning of a write operation of a semiconductor memory device to a timing when a read and/or write operation may be enabled. In other words, the tWR may be defined as a period of time from the beginning of the last data write to the receipt of a precharge command signal, that is, last data_in to row_precharge (Last data_in to row_precharge; Write Recovery Time).
The tWR may include a column select line (CSL) enable time, during which a CSL signal may be activated and valid write data may be applied to a bit line, and an active restore time, during which the CSL signal may be deactivated and valid write data may be stored in a memory cell until a word line may be precharged.
FIG. 1 is a block diagram illustrating an example of the control of a column select line signal in a related art semiconductor memory device.
As illustrated in the FIG. 1, column select line enable signal PCLKCD may be activated by an internal clock signal PCLK which may be generated from a master clock signal CLK and/or the write enable signal PWR. A column select line disable signal PCSLP may transition from a first logic state (for example, a ‘high’ logic state) to a second logic state (for example, a ‘low’ logic state) in response to the internal clock signal PCLK and/or a precharge enable signal.
When the column select line enable signal PCLKCD may be activated, the column line select signal CSL may be activated. When the column select line disable signal PCSLP may transition from the first logic state (for example, a ‘high’ logic state) to the second logic state (for example, a ‘low’ logic state), the column line select signal CSL may be deactivated.
The write enable signal PWR may be activated by a write command signal WRITE which may define a write operation among a plurality of input command signals. The precharge enable signal may be activated by a precharge command signal PRE which may define a precharge operation among the plurality of input command signals.
FIG. 2 is a diagram illustrating an example of a circuit which may provide the column select line signal CSL in a related art semiconductor memory device.
The circuit may include a first PMOS transistor MP1 which may receive the column select line enable signal PCLKCD, an NMOS transistor MN3 which may receive the column select line enable signal PCLKCD, a second PMOS transistor MP2 which may receive the column select line disable signal PCSLP and may be connected between the first PMOS transistor MP1 and the NMOS transistor MN3, a first inverter 51 which may be connected to a node where the second PMOS transistor MP2 and the NMOS transistor MN3 may be connected to each other, and a second inverter 52 which may be connected to the first inverter 51 in a latch configuration.
When the column select line enable signal PCLKCD may be activated, the first PMOS transistor MP1 may be turned off and the NMOS transistor MN3 may be turned on, such that an input terminal of the first inverter 51 may be electrically connected to an electrode (for example, a ground electrode). The input terminal of the first inverter 51 may be in a second logic state (for example, a ‘low’ logic state), and therefore the column line select signal CSL may be activated.
When the column select line disable signal PCSLP may be in a first logic state (for example, a ‘high’ state), the first PMOS transistor MP1 may be turned off and may not supply charges to the input terminal of the first inverter 51. When the column select line disable signal PCSLP may be in the second logic state (for example, a ‘low’ logic state) and the column select line enable signal PCLKCD may be in the second logic state (for example, a ‘low’ logic state), the first PMOS transistor MP1 and the second PMOS transistor MP2 may be turned on, and the NMOS transistor MN3 may be turned off. As a result, the input terminal of the first inverter 51 may be electrically connected to a power supply voltage electrode. Charges may be supplied to the input terminal of the first inverter 51, such that the input terminal of the first inverter 51 may be in the first logic state (for example, a ‘high’ state) and the column line select signal CSL may be deactivated.
Since the second inverter 52 may be connected to the first inverter 51 in a latch configuration, the column line select signal CSL may not float due to charge sharing at the node where the second PMOS transistor MP2 and the NMOS transistor MN3 may be connected to each other. When a signal may float, it may not be determined whether the signal may be in the first logic state (for example, a ‘high’ state) or the second logic state (for example, a ‘low’ logic state).
For synchronous semiconductor devices, the tWR may be expressed by the number of clock cycles, for example, tWR=2 clock cycles, or tWR=3 clock cycles. High-speed synchronous semiconductor memory devices may have a tWR of a few clock cycles.
To test a write operation of a high-speed synchronous semiconductor memory device which may have a tWR of a few clock cycles, the test may need to be performed at the same, or substantially the same frequency as the write frequency of the high-speed synchronous semiconductor memory device which may be used to examine a state of the write operation.
Considering the fact that progress may be being made in this field, it may not be cost-effective to develop testing equipment every time progress may be made. Therefore, it may be economical to use related art testing equipment which may be used to detect write failures in a write operation test.
A problem with the related art write control method which may be used for the write operation test may be that write failures may not be accurately detected, and the throughput of semiconductor memory devices may not be increased.